The present invention is directed to integrated circuits. More particularly, the invention provides a device and method for low non-linearity analog-to-digital converter. Merely by way of example, the invention has been applied to a successive approximation register (SAR) analog-to-digital converter (ADC). But it would be recognized that the invention has a much broader range of applicability.
The successive approximation register (SAR) analog-to-digital converter (ADC) is widely used for analog-to-digital conversion. The analog-to-digital conversion uses a binary search to digitize an analog signal to a digital signal. The analog signal generates an analog voltage which is compared to an effective reference voltage generated by the SAR ADC. The SAR ADC uses a resistor string or/and a capacitor array to generate the effective reference voltage. Based on comparison between the analog voltage and the effective reference voltage, the effective reference voltage is adjusted and again compared with the analog voltage. Through iterations, the binary search narrows down the digital range until the bit length is reached.
FIG. 1 is a simplified diagram for SAR ADC. A SAR ADC 100 uses both a capacitor array and a resistor string to generate an effective reference voltage. The capacitor array is used for 3 Most Significant Bits (MSBs), and the resistor string is used for 3 Least Significant Bits (LSBs). The resistor string can be connected only to a capacitor 116, and the voltage on the capacitor 116 can be multiples of ⅛ of a reference voltage (Vref) 130. An input analog voltage (Vin) 140 is sampled at the bottom of capacitors 110, 112, 114 and 116 with an op-amp 120 closed. Then the op-amp 120 is opened and one of voltages 132, 134 and 136 is applied to each of the capacitors 110, 112, 114 and 116. The voltage 136 is at the ground level. The effective capacitance connected to Vs is decided by a SAR-controlled process and includes the effective capacitance of the capacitor 116. The effective capacitance of the capacitor 116 equals the capacitance of the capacitor 116 multiplied by m/8 when a switch (150+2m) is closed. The effective reference voltage equals Vref multiplied by the ratio of effective capacitance to total capacitance. The total capacitance is the sum of capacitance for the capacitors 110, 112, 114 and 116.
As shown in FIG. 1, the capacitors 114 and 116 are designed to have the same capacitance. The capacitor 110 should have four times of capacitance as the capacitor 114 or 116, and the capacitor 112 should have twice as much as capacitance as the capacitor 114 or 116. Additionally, resistors 170, 172, 174, 176, 178, 180, 182, and 184 should have the same resistance. These design specifications may not be fully implemented in a fabricated SAR ADC. For example, the fabricated SAR ADC may have slightly different capacitance for the capacitors 114 and 116. These mismatches of individual resistors or capacitors can adversely affect the linearity of the SAR ADC and quality of the analog-to-digital conversion.
From the above, it is seen that an improved technique for analog-to-digital conversion is desired.